module divider(
iClk, // input clock
iReset, // reset signal
iReady, // indicates inputs are ready
oDone, // indicates that the result is ready
iDividend, // 16-bit multiplier [15:0]
iDivisor, // 8-bit multiplicand [7:0]
oQuotient, // 8-bit quotient [15:0]
oReminder, // 8-bit reminder [7:0]
);

input iClk, iReset, iReady;
input [15:0] iDividend;
input [7:0] iDivisor;

output oDone;
output [15:0] oQuotient=0;
output [7:0] oReminder;

reg [7:0] oReminder;
reg [15:0] oQuotient; //there is not integrated register, like [23:0]. just operating individually & dependently
reg [3:0] counter=0;
reg oDone=0;
reg [1:0]save; //save bit for unshift

initial begin //initializing : shift left R(=oReminder|oQuotient)
oReminder={7'b000_0000, iDividend[15]};
oQuotient={iDividend[14:0],1'b0};
end

always @ (iReset) begin
oReminder=0;
oQuotient=0;
oDone=0;
end

always @ (posedge iClk & !(oDone) & iReady & !(iReset)) begin

oReminder=oReminder-iDivisor; //Rem=Rem-div
if(oReminder[7]) begin //if Rem<0
oReminder=oReminder+iDivisor; //restore Rem
oReminder={oReminder[6:0], oQuotient[15]}; //shift left R(=oReminder|oQuotient), R0=0
oQuotient={oQuotient[14:0], 1'b0};
end
else begin //if Rem>0
oReminder={oReminder[6:0], oQuotient[15]}; //shift left R(=oReminder|oQuotient), R0=1
oQuotient={oQuotient[14:0], 1'b1};
end
if(counter==15) begin //counting
oDone=1;
oReminder={1'b0, oReminder[7:1]}; //unshift oReminder
end

counter=counter+1;
end
endmodule
